Vertical access transistor with curved channel

ABSTRACT

An access transistor ( 140 ) for a vertical DRAM device ( 110 ) and method of forming thereof. Trenches ( 114 ) are formed in a semiconductor wafer substrate ( 112 ), and storage capacitors ( 118 ) are formed in the bottom portion of the trenches ( 114 ). The trenches ( 114 ) are curved in a channel ( 130 ) region formed in a top portion of the trenches ( 114 ). The channel ( 130 ) is curved about a central point c, and the channel extends into the substrate ( 112 ) by a distance d along a radius b. A gate oxide ( 126 ) is disposed adjacent the curved channel ( 130 ), and a gate conductor ( 128 ) is disposed adjacent the gate oxide ( 126 ).

TECHNICAL FIELD

The present invention relates generally to the fabrication of integratedcircuits (IC's), and more particularly to the fabrication of memoryIC's.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications,such as personal computers and cellular phones, for example. One suchsemiconductor product widely used in electronic systems for storing datais a semiconductor memory, and a common type of semiconductor memory isa dynamic random access memory (DRAM).

A DRAM typically includes millions or billions of individual DRAM cellsarranged in an array, with each cell storing one bit of data. A DRAMmemory cell typically includes an access field effect transistor (FET)and a storage capacitor. The access FET allows the transfer of datacharges to and from the storage capacitor during reading and writingoperations. In addition, the data charges on the storage capacitor areperiodically refreshed during a refresh operation.

DRAM storage capacitors are typically formed by etching deep trenches ina semiconductor substrate, and depositing and patterning a plurality oflayers of conductive and insulating materials over the substrate inorder to produce a storage capacitor that is adapted to store data,represented by a one or zero. Prior art DRAM designs typically comprisean access FET disposed in a subsequently deposited layer, disposed aboveand to the side of the storage capacitor.

The semiconductor industry in general is being driven to decrease thesize of semiconductor devices located on integrated circuits.Miniaturization is generally needed to accommodate the increasingdensity of circuits necessary for today's semiconductor products.Decreasing the size of DRAM's creates manufacturing challenges.

More recent DRAM designs involve disposing the access FET directly abovethe storage capacitor, sometimes referred to as a vertical DRAM, whichsaves space by conserving surface area, and results in the ability toplace more DRAM cells on a single chip. In vertical DRAM technology, theaccess FET is positioned vertically at the upper part of a deep trench.

SUMMARY OF THE INVENTION

Embodiments of the present invention achieve technical advantages as avertical access transistor for a semiconductor memory device having acurved channel. By using the curved channel in accordance withembodiments of the invention, a variety of parameters of the FET may bealtered, such as increasing or decreasing the threshold voltage and/orbody factor, without changing the doping diffusion or requiringadditional masking steps for additional diffusions.

In one embodiment, a semiconductor memory device includes asemiconductor wafer having a surface, and a plurality of trenches formedin the semiconductor wafer, the trenches including a top portion. Avertical access transistor is formed in the trench top portion, whereinthe transistor includes a channel disposed substantially perpendicularto the semiconductor wafer surface, and wherein the channel is curved.

In another embodiment, a vertical access transistor for a semiconductormemory device includes a curved channel.

In another embodiment, a method of forming a vertical access transistorfor a memory device includes providing a semiconductor wafer, andforming a plurality of trenches in the semiconductor wafer. The trenchesinclude a top portion, and the trench top portion has a curved channelregion for the vertical access transistor.

Advantages of embodiments of the invention include increasing ordecreasing the threshold voltage and body factor of the transistorwithout affecting other parameters or changing process steps. The curvedchannel may be used to change the electric field at the gate oxide,e.g., to improve reliability. Furthermore, manufacturability isimproved, by providing more flexibility in the selection of gate oxidethickness and channel doping levels.

BRIEF DESCRIPTION OF THE DRAWINGS

The above features of embodiments of the present invention will be moreclearly understood from consideration of the following descriptions inconnection with accompanying drawings in which:

FIG. 1 shows a cross-sectional view of a prior art vertical DRAM accesstransistor;

FIG. 2 shows a top view of the vertical DRAM access transistor shown inFIG. 1 a;

FIG. 3 shows a top view of an embodiment of the present inventionwherein the vertical access transistor has a concave curved channel;

FIG. 4 a shows a top view of an embodiment having a convex curvedchannel vertical access transistor;

FIG. 4 b shows a top view of an embodiment wherein a portion of thesubstrate at the top of the trench is removed prior to forming theconvex curved channel vertical access transistor;

FIG. 5 is a cross-sectional view of the embodiment shown in FIGS. 4 aand 4 b;

FIG. 6 shows a top view of another embodiment having a concave curvedchannel vertical access transistor;

FIG. 7 shows a top view of an embodiment wherein additional material isadded to the trench sidewall prior to forming a concave curved channelvertical access transistor; and

FIG. 8 illustrates a cross-sectional view of the embodiment shown inFIG. 7.

Corresponding numerals and symbols in the different figures refer tocorresponding parts unless otherwise indicated. The figures are drawn toclearly illustrate the relevant aspects of the preferred embodiments andare not necessarily drawn to scale.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Prior art vertical DRAMs will be discussed, followed by a description ofsome preferred embodiments of the present invention and some advantagesthereof. One memory cell is shown in each figure, although many othermemory cells and components of memory cells may be present in thesemiconductor devices shown.

FIG. 1 shows a cross-sectional view of a prior art vertical DRAM 10having a channel 24 positioned vertically, on the sidewall of an etchedtrench 14 above a deep trench capacitor 18. The deep trench 14 is linedwith an insulator 16 prior to depositing the capacitor 18 material. Thetransistor current is conducted in a direction perpendicular to thewafer surface 11 through the vertical channel 24, rather than parallelto the surface 11, as in horizontal MOSFET transistors.

The vertical transistor 10 shown in FIG. 1 comprises a NMOS-typetransistor, for example. FIG. 2 shows a top view of the etched trenchshown in FIG. 1. The transistor is similar to a conventional horizontalNMOS transistor, with an n-doped source 20 disposed near the top surfaceof the substrate 12, and an n-doped drain 22 disposed beneath thechannel 24. The drain 22 is also often referred to as a buried strap,for example. The trench 14 sidewall includes the p-doped channel 24disposed between the source 20 and drain 22. A gate oxide 26 is disposedadjacent the channel 24. A gate conductor 28 comprising a polysiliconmaterial, for example, is disposed adjacent the gate oxide 26.Alternatively, a single gate conductor 29 may be disposed adjacent thegate oxide, extending between the two gate oxides 26 on either side ofthe trench sidewalls, as shown in phantom. The properties of a verticaltransistor 10 are similar to those of a conventional horizontaltransistor with similar dimensions and diffusion properties.

The gate 28, gate oxide 26, and channel 24 of prior art vertical accessFETs 10 are substantially rectangular in shape, as shown. While thetrench 14 is substantially elliptical or oval in shape, the trenchsidewalls are relatively straight in the region where the verticalaccess transistor 10 is formed. The width d indicated with a dashed lineindicates the width of the depletion region or channel inside thep-silicon. In order to change the properties of prior art vertical FETs,the diffusion concentration must be changed, requiring additionalmanufacturing steps and mask levels.

Embodiments of the present invention achieve technical advantages as aDRAM having a vertical access transistor with a curved channel. Thevertical access transistor channel is either convex or concave, whichallows various properties of the transistor to be varied. The trenchsidewalls may be curved prior to forming the gate oxide and gate of thevertical transistor. For example, the design of the trench itself may becurved, material may be added that is curved to the trench sidewall, ormaterial may be removed from the trench sidewall to create the curve, tobe discussed further herein.

FIG. 3 shows a top view of a memory device having a vertical accesstransistor 110 with a concave curved channel 130 in accordance with anembodiment of the present invention. The term “concave”, as used herein,refers to a curve in a channel that curves inwardly toward the center ofthe trench 114. In this embodiment, the trench 114 comprises a shapewherein the sidewalls are curved in the region where the gate oxide 126and gate conductor 128 will be formed.

A preferred process for manufacturing the vertical DRAM device 110 ofFIG. 3 will next be described. A semiconductor wafer workpiece 112comprising a substrate is provided. The workpiece 112 typicallycomprises a semiconductor material such as single-crystal silicon, andmay include other conductive layers or other semiconductor elements suchas transistors or diodes, as examples. The workpiece 112 mayalternatively comprise semiconductors such as GaAs, InP, Si/Ge, SiC, orother compound semiconductors, as examples.

A pad nitride, not shown, may be deposited over the semiconductorsubstrate 112. The pad nitride preferably comprises silicon nitridedeposited in a thickness of 100-300 nm, as an example. Alternatively,the pad nitride may comprise other nitrides or oxides, as examples.

A plurality of trenches 114 is formed in the workpiece 112. The trenches114 may have a high aspect ratio, e.g., the depth may be much greaterthan the width. For example, trenches 114 may be 100 nm wide and 10 μmdeep below the top surface of the workpiece 112. The trenches 114preferably have an oval or elliptical shape when viewed from the topsurface of the wafer, although the trenches 114 may comprise othershapes. The trenches 114 form storage nodes or capacitors of memorycells, such as in a DRAM, for example.

A buried plate is formed, and a node dielectric is formed, not shown.The trenches are filled with collar oxide, and the trenches are filledwith a semiconductor material 118 such as polysilicon, to form thecapacitor inner plate and buried strap. The semiconductor material 118is etched back to a predetermined distance below the workpiece 112surface.

An insulating material is deposited over the polysilicon within thetrench to cover the sidewalls. The insulating material preferablycomprises an oxide such as SiO₂, as an example. A conductive materialsuch as a semiconductor material is deposited over the insulatingmaterial. The conductive material may comprise polysilicon, for example,although other conductive materials may be used. The semiconductormaterial and insulating material are patterned and etched to form gateconductor 128 and gate oxide 126, respectively, adjacent the curvedchannel 130. The gate conductor 129 may alternatively extend between thetwo gate oxides 126 on either side of the trench 114, as shown inphantom.

In this embodiment, the trenches 114 are designed such that thesidewalls are curved in the region 132 where the gate oxide 126 and gate128 will be formed. The curved substrate 112 creates a curved channeland depletion layer 130. The structure shown in FIG. 3 illustrates aconcave channel 130 having a width d.

Advantageously, the curved channel 130 in accordance with embodiments ofthe present invention results in a different threshold voltage and bodyfactor than the threshold voltage and body factor for a prior artstraight channel structure shown in FIGS. 1 and 2. The body factor isthe sensitivity of a transistor 140 when a voltage is applied from thebody, e.g., the substrate 112. For a concave channel 130 shown in FIG.3, the effect of the curvature on the NMOS properties can be understoodqualitatively as the effect of an electric field increase, as in thecase of a sharp conducting tip. Furthermore, a concave channel 130results in an effective increase of the doping level (e.g., the chargewithin the region) within the depletion region d.

Thus, a concave channel 130 results in an increase in the thresholdvoltage and body factor of the transistor. A concave channel 130 alsoincreases the electric field at the oxide/silicon interface.

An analysis of the effect of a concave curved channel 130 in accordancewith embodiments of the present invention on the transistor 140 willnext be discussed. A numerical calculation may be used to determine thechange in threshold voltage and body factor as a result of the curvedchannel 130 of embodiments of the present invention. Referring to FIG.3, the radius of curvature from a center point c of the curve to theoxide/silicon interface is indicated by distance a. The radius ofcurvature from the center point c to the outer edge of the channel 130having a width d is indicated by distance b.

For the depletion layer 130 of a MOSFET, the relationship between thepotential and the electric field can be represented by Equation 1:d ² V/dx ² =dE/dx=qN/∈,  Eq. 1:where V is the potential, E is the electric field, q is the elementarycharge, N is the doping concentration in the silicon and ∈ is thedielectric constant of the substrate 112 material, e.g., silicon.

For a transistor 140 having a concave channel 130, the electric field Emay be calculated by Equation 2: $\begin{matrix}{{{\text{Eq.~~2:}\quad E} = {{\int{{{\mathbb{d}E}/{\mathbb{d}x}}\quad{\mathbb{d}x}}} = {{1/a}\quad{\int{q\quad N\quad{r/ɛ}\quad{\mathbb{d}\quad r}}}}}},\text{or:}} & \quad \\{{\text{Eq.~~3:}\quad = {{1/a}\quad q\quad{N/{ɛ\quad\left\lbrack {\left( {b^{2} - a^{2}} \right)/2} \right\rbrack}}}},} & \quad\end{matrix}$where a represents a radius from a center point c of the curve to theoxide/silicon interface, and b represents the radius from the curvecenter point c to the edge of the depletion layer or channel 130 in thesubstrate 112, as illustrated in FIG. 3.

The potential is the integral of the field, represented by Equation 4:$\begin{matrix}{{{\text{Eq.~~4:}\quad\Psi} = {{\int{E{\mathbb{d}r}}} = {{\int{{1/a}\quad q\quad{N/{ɛ\left\lbrack {\left( {r^{2} - a^{2}} \right)/2} \right\rbrack}}{\mathbb{d}r}}}\quad = {{1/a}\quad q\quad{N/{ɛ\quad\left\lbrack {{{1/6}\quad r^{3}} - {{1/2}\quad r\quad a^{2}}} \right\rbrack}_{a}^{b}}}}}},\text{or:}} & \quad \\{\text{Eq.~~5:}\quad = {q\quad{N/ɛ}\quad{\left( {{{1/6}\quad{b^{3}/a}} - {b\quad{a/2}} + {a^{2}/3}} \right).}}} & \quad\end{matrix}$

If the depletion layer width d is much smaller than the radius a, then:b=a+d=>Ψ=qN/∈(d ³/6a+d ²/2).  Eq. 6:

At threshold, the potential is equal to twice the flatband voltageφ_(f), and the depletion layer thickness d_(th) may be determined byEquation 7:

 d _(th) : qN/∈(d ³/6a+d ²/2)=2φ_(f).  Eq. 7:

The voltage over the oxide is given by Equation 8:V _(ox) =K√(2φ_(f)).  Eq. 8:

If d<<a, the body factor K is approximately equal to that shown inEquation 9:K≈1/C _(ox)(√(2∈qN)+√(2φ)∈/a);  Eq. 9:where C_(ox) is the capacitance of the gate oxide 126, which can becalculated by C_(ox)=∈A/t, where A is the area of the gate oxide 126 andt is the thickness of the oxide. The body factor K for a concave channel130 is higher than the body factor K for a conventional, flat (e.g.,straight) channel, which may be calculated by Equation 10:K=1/C _(ox)√(2∈qN)  Eq. 10:

The equations may be solved numerically, e.g., without the need ford<<a. In a typical example, with a gate oxide 126 thickness comprising6.6 nm, and having a channel 130 doping concentration in the channel of7.10¹⁷ cm⁻³ and a radius of curvature b of 100 nm, the calculationsyield a body factor K of 1.02 V^(1/2) and a threshold voltage V_(th) of0.42 V. A comparable conventional, flat channel would have a body factorK of 0.92 V^(1/2) and a threshold voltage V_(th) of 0.34 V, for example.Therefore, the body factor and threshold voltage may be increased usinga vertical access transistor 140 having a concave curved channel 130 asshown in FIG. 3, in accordance with an embodiment of the presentinvention.

An embodiment of a vertical access transistor 240 having a convex curvedchannel 230 is shown in a top view in FIG. 4 a. Preferably, when thetrench 214 is formed using lithography, the trench 214 shape includes aconvex curved channel 230. Thus, no additional processing steps arerequired to produce the curved channel 230. Gate oxide 226 and gateconductor 229 are formed adjacent the channel 230. In the embodimentshown, gate conductor 229 extends completely between the gate oxides 226on either side of the trench 214. Alternatively, the gate conductor maynot extend completely between the gate oxides 226, for example.

The gate oxide 226 and the gate conductor 228 also comprise a convexcurve, e.g., the channel 230, gate oxide 226 and gate conductor 229curve outwardly away from the trench 214 about a center point c. Theradius of curvature b comprises the width d of the channel 230 ordepletion region and the distance a between the center point c of thecurve and the edge of the channel 230.

Alternatively, to form the curved channel 230, a portion of thesubstrate 212 may be removed e.g. at 234, as shown in FIG. 4 b. Similarto the process described for FIG. 4 a, gate oxide 226 and gate conductor228 are formed adjacent the channel 230. The gate oxide 226 and the gateconductor 228 also comprise a convex curve, e.g., the channel 230, gateoxide 226 and gate conductor 228 curve outwardly away from the trench214 about a center point c. In the embodiment shown, gate conductor 228does not extend completely between the gate oxides 226, althoughalternatively, the gate conductor may extend completely between the gateoxides 226, as shown in FIG. 4 a. Again, the radius of curvature bcomprises the width d of the channel 230 or depletion region and thedistance a between the center point c of the curve and the edge of thechannel 230.

The equations for a vertical access transistor 240 having a convexcurved channel 230 are similar to those for a concave curved channel 130of FIG. 3, but with a different sign. For example, the potential may becalculated using Equation 11:Ψ=qN/∈(d ²/2−d ³/6a)  Eq. 11and the body factor can be calculated using Equation 12:K≈1/C _(ox)(√(2∈qN)−√(2φ)∈/a)  Eq. 12:

FIG. 5 shows a cross-sectional view of the embodiments shown in FIGS. 4a and 4 b. The n-type regions 220 and 222 may comprise source/drainregions, respectively. Channel 230 may be doped with p-type material. Astorage capacitor (not shown) is formed in the lower portion of thetrench 214.

For a convex channel 230, shown in FIGS. 4 a and 4 b, for a radius ofcurvature b of 100 nm, the calculations yield a body factor K of 0.80V^(1/2) and a threshold voltage V_(th) of 0.25 V. Therefore, comparingthese values to those of a conventional, flat channel, the body factorand threshold voltage may be decreased using a convex curved channel.

FIG. 6 shows a top view of another embodiment of the present inventionhaving a concave curved channel vertical access transistor 340. In thisembodiment, a portion of the substrate 312 is removed to form a curvedarea 334, and the gate oxide 326 and gate conductor 328 are formedadjacent the substrate curved area 334. The same Equations apply asEquations 1 through 10 described above for FIG. 3.

In another embodiment 410 of the invention, shown in a top view in FIG.7, semiconductor material 436 may be added to the substrate 412 prior toforming the curved channel region 430. For example, silicon material 436may be grown over the trench 414 sidewalls after other areas are maskedwith an oxide. An excess amount of additional material 436 may bedeposited, and then etched to produce the desired shape and thickness,for example. FIG. 8 illustrates a cross-sectional view of the embodiment410 shown in FIG. 7.

Similar to the other embodiments described herein, the gate conductor328/428 may alternatively extend completely between the gate oxides326/426 for the embodiments shown in FIGS. 6-8 (not shown).

Further processing is continued to complete the vertical DRAM110/210/310/410 device. For example, an insulating material may bedeposited to fill the trenches 114/214/314/414 and form shallow trenchisolation (STI). Subsequent material layers may be deposited andpatterned.

Preferably, the radius of curvature b is selected such that the effecton the body factor K is between about −0.04 to −0.20 V^(1/2), forexample, for a convex channel, and about +0.02 to +0.20 V^(1/2), forexample, for a concave channel. The effect on the threshold voltageV_(th) is preferably between about −0.015 to −0.18 V, as examples (for aconvex channel), and preferably between about +0.03 to +0.15 V, asexamples (for a concave channel). Furthermore, in accordance withembodiments of the invention, the radius of curvature b is preferablybetween about 60 to 250 nm (for a convex channel), and preferablybetween about 50 to 300 nm (for a concave channel), as examples.

Embodiments of the present invention achieve technical advantages byproviding a curved channel 130/230/330/340 that is adapted to increaseor decrease the threshold voltage and body factor of a vertical accesstransistor 140/240/340/440. The concave channel 130/330/340 describedherein also results in an increased electric field at the oxide/siliconinterface.

A vertical transistor having a curved channel provides more freedom indesigning devices with specific properties for designs of memory cellsor other applications. For example, the threshold voltage may be changedwithout changing the channel doping. Devices with different thresholdvoltages may be manufactured without requiring additional masking stepsfor additional diffusions. Advantageously, the electric field may bechanged at the gate oxide to improve reliability. Manufacturability isimproved because of the increased flexibility in selecting the gateoxide thickness and/or channel doping level, provided by embodiments ofthe present invention.

Furthermore, because the channel 130/230/330/430 resides on the sidewallof the trench 114/214/314/414, rather than on the surface of a wafer, asin horizontal DRAM technology, the channel 130/230/330/430 may be shapedinto a curved shape, in accordance with embodiments of the presentinvention.

While embodiments of the present invention are described herein withreference to DRAM devices, they also have useful application in othersemiconductor devices. Embodiments of the present invention haveapplication in memory devices utilizing N-MOSFET and P-MOSFET typetransistors, as examples. Embodiments of the invention may also be usedin other structures where the technology allows formation of a curvedchannel, for instance if a vertical structure is formed on top of asemiconductor wafer.

While the invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications in combinations of theillustrative embodiments, as well as other embodiments of the invention,will be apparent to persons skilled in the art upon reference to thedescription. In addition, the order of process steps may be rearrangedby one of ordinary skill in the art, yet still be within the scope ofthe present invention. It is therefore intended that the appended claimsencompass any such modifications or embodiments. Moreover, the scope ofembodiments of the present application is not intended to be limited tothe particular embodiments of the process, machine, manufacture,composition of matter, means, methods and steps described in thespecification. Accordingly, the appended claims are intended to includewithin their scope such processes, machines, manufacture, compositionsof matter, means, methods, or steps.

1. A memory device comprising: a semiconductor wafer having a surface; aplurality of trenches formed in the semiconductor wafer, each trenchincluding a top portion, and each trench having a first sidewall that isconvexly curved and a second sidewall that is not convexly curved; aplurality of vertical access transistors, each transistor formed in thetop portion of one of the trenches, wherein the transistor includes acurved channel disposed substantially perpendicular to the semiconductorwafer surface and wherein each vertical access transistor comprises asource region and a drain region formed in the semiconductor waferdisposed along the convexly curved sidewall of the trench, eachtransistor further including a gate insulating layer formed only alongthe convexly curved sidewall of the trench and a gate conductor formedin contact with the gate insulating layer, wherein the curved channel isdisposed vertically between the source and drain regions and along theconvexly curved sidewall of the trench so that the channel is convex. 2.The memory device according to claim 1, wherein each trench include abottom portion disposed beneath the trench top portion, the memorydevice further comprising a storage capacitor formed in each trenchbottom portion.
 3. The memory device according to claim 2, wherein eachstorage capacitor comprises a dynamic random access memory (DRAM)storage cell.
 4. The memory device according to claim 1, wherein thegate insulating layer comprises a gate oxide.
 5. The memory deviceaccording to claim 1, wherein the channel has a radius of curvature isbetween about 60 to 250 nm.
 6. A vertical transistor, comprising: asemiconductor wafer having a surface; and a vertical transistor formedin the semiconductor wafer, the vertical transistor including a sourceregion proximate to the wafer surface and a drain region verticallyspaced from the wafer surface, the transistor further including a curvedchannel having a depletion width located within the semiconductor wafersubstantially perpendicular to the semiconductor wafer surface betweenthe source region and the drain region, and wherein the channel isconvex and has a radius of curvature that is substantially greater thanthe depletion layer width so that the vertical transistor has athreshold voltage of not more than 0.25V.
 7. A vertical transistorcomprising: a semiconductor wafer having a surface; at least one trenchformed in the semiconductor wafer, the trench including a top portion,wherein the vertical transistor is formed in the top portion of thetrench; a curved channel disposed within the semiconductor wafer andsubstantially perpendicular to the semiconductor wafer surface whereinthe curved channel is concave and has a radius of curvature and adepletion layer width that is much smaller than the radius of curvatureso that the transistor has a body factor of at least 1.02 V^(1/2) and athreshold voltage of at least 0.42V; a source region formed in thesemiconductor wafer proximate the wafer surface above the curved channeland along a sidewall of the trench; and a drain region formed in thesemiconductor wafer below the curved channel, wherein the curved channelis disposed vertically between the source and drain regions.
 8. Thevertical transistor according to claim 7, wherein the trench includes abottom portion disposed beneath the trench top portion, furthercomprising a storage capacitor formed in the trench bottom portion. 9.The vertical transistor according to claim 8, wherein the storagecapacitor comprises a dynamic random access memory (DRAM) storage cell.10. The vertical transistor according to claim 7, wherein the radius ofcurvature is between about 50 to 300 nm.
 11. The vertical transistoraccording to claim 7, wherein the vertical transistor includes a gateoxide disposed adjacent the curved channel, and a gate conductordisposed adjacent the gate oxide.
 12. A dynamic random access memory(DRAM) cell comprising: a trench formed in a semiconductor region, thetrench having a cross-sectional shape of an oval or an ellipse; astorage capacitor disposed in a lower portion of the trench; a firstgate insulating layer portion disposed adjacent one sidewall of thetrench and a second gate insulating layer portion disposed adjacent anopposite sidewall of the trench, the first gate insulating layer portionbeing separated from the second gate insulating layer portion; a gateregion disposed within a portion of the trench above the storagecapacitor, the gate region extending between the first gate insulatinglayer portion and the second gate insulating layer portion; a sourceregion disposed in the semiconductor region along a sidewall of thetrench, the source region being electrically coupled to the storagecapacitor; a channel region disposed in the semiconductor region alongthe sidewall of the trench, the channel region being adjacent the gateregion, the channel region being curved; and a drain region disposed inthe semiconductor region along the sidewall of the trench so that thecurved channel region is disposed vertically between the source regionand the drain region.
 13. The DRAM of claim 12, wherein thesemiconductor region comprises a semiconductor substrate.
 14. The DRAMcell of claim 12, wherein the radius of curvature is between about 50 nmto about 300 nm.